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SP9840/43
8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC
s Replaces 8 Potentiometers and 8 Op amps s Operates from Single +5V Supply s 5 MHz 4-Quadrant Multiplying Bandwidth s Eight Inputs/Eight Outputs (SP9840) Four Inputs/Eight Outputs (SP9843) s 3-Wire Serial Input s 0.8MHz Data Update Rate s +3.25V Output Swing s Midscale Preset s Programmable Signal Inversion s Low 70mW Power Dissipation (9mW/DAC) DESCRIPTION... The SP9840 and SP9843 are general purpose octal DACs in a single package. The SP9840 features eight individual reference inputs, while the SP9843 provides four pair of voltage reference inputs. Both parts feature 5MHz bandwidth, four-quadrant multiplication, and a three- wire serial interface. Other features include midscale preset, programmable signal inversion and low power dissipation from a single +5V supply. Devices are available in commercial and industrial temperature ranges.
VIN1
-
8 Data Clock Serial Data Input Serial Data Output Preset SERIAL REGISTER 8 8x8 DAC REGISTER 8 8 Decoded Address
+
VOUT1 DAC 1
4 LOGIC
Load
VIN8 VOUT8 DAC 8 VREF Low
SP9840 shown
257
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VDD to GND ...................................................................... -0.3V, +7V VINX to GND ............................................................................... VDD VREFL to GND ............................................................................. VDD VOUTX to GND ............................................................................ VDD Short Circuit IOUTX to GND ............................................ Continuous Digital Input & Output Voltage to GND ....................................... VDD Operating Temperature Range Commercial ............................................................... 0C to +70C Extended Industrial ................................................. -40C to +85C Maximum Junction Temperature (TJ max) .......................... +150C Storage Temperature ................................................. -65 to 150C Lead Temperature (Soldering, 10 sec) ............................... +300C Package Power Dissipation .................................. (TJ max - TA)/8JA Thermal Resistance 8JA P-DIP .................................................................................. 57C/W SOIC-24 .............................................................................. 70C/W CAUTION: While all input and output pins have internal protection networks, these parts should be considered ESD (ElectroStatic Discharge) sensitive devices. Permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Personnel should be properly grounded prior to handling this device. The protective foam should be discharged to the destination socket before devices are removed.
SPECIFICATIONS
(VDD = +5V, All VINX= 0V, VREFL = 1.625V, TA = 25 C for commercial-grade parts; TMIN TA = TMAX for industrial-grade parts; specifications apply to all DAC's unless noted otherwise.)
PARAMETER SIGNAL INPUTS Input Voltage Range Input Resistance SP9840 SP9843 Input Capacitance SP9840 SP9843 VREFL Resistance VREFL Capacitance DIGITAL INPUTS Logic High Logic Low Input Current Input Capacitance Input Coding STATIC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Half-Scale Output Voltage Minimum Output Voltage Output Voltage Drift DYNAMIC PERFORMANCE Multiplying Gain Bandwidth Slew Rate Positive Negative Total Harmonic Distortion Output Settling Time Crosstalk Digital Feedthrough Wideband Noise SINAD Digital Crosstalk
MIN. 0 3.1 1.55
TYP.
MAX. 3.25
UNITS V k k
CONDITIONS VDD = 4.75V, VREFL = 1.625V D = 2BH, Code Dependent Note 1
6.2 3.1 19 38 1.3 190 30 60 250
0.68
pF pF k pF V V A pF
Note 1 and 2 Note 1
2.4 0.8 10 8 Offset Binary 8 0.75 0.3 1.625 20 25 5 7.9 -8.3 0.003 0.7 70 6 42.5 89 6
Note 3 Bits LSB LSB V mV V/C MHz V/s V/s % s dB nVs Vrms dB nVs
1.600
1.5 1 1.650 100
Note 4 Note 4 PR = LOW, VREFL = 1.625V D=FFH; ISINK = 0.1mA PR = LOW VIN(X) = 100mVP-P + 1.625V dc Measured 10% to 90% V = 3.2V V = -3.2V VIN(X) = 3VP-P +1.625V dc, D=FFH; 1KHz, fLP=80KHz 1 LSB Error Band Note 5 D = 0H to FFH VOUT = 3.25V, 400Hz to 80kHz VIN(X) = 3VP-P +1.625V dc, D=FFH; 1KHz, fLP=80KHz Note 6
3 3.0 -3.0
60
258
SPECIFICATIONS (continued)
VDD = +5V, All VINX= +0V, VREFL = 1.625, TA = 25 C for commercial-grade parts; TMIN TA = TMAX for industrial-grade parts; specifications apply to all DAC's unless noted otherwise.)
PARAMETER MIN. TYP. MAX. DAC OUTPUTS Voltage Range 0 VDD - 1.5 Output Current 10 15 Capacitive Load 47,000 DIGITAL OUTPUT Logic High 3.5 Logic Low 0.4 POWER REQUIREMENTS Power Supply Range 4.75 5.00 5.25 Positive Supply Current 14 Power Dissipation 70 ENVIRONMENTAL AND MECHANICAL Operating Temperature Range Commercial 0 +70 Industrial -40 +85 Storage Temperature Range -65 +150 Package SP9840N 24-pin, 0.3" Plastic DIP SP9840S 24-pin 0.3" SOIC SP9843S 20-pin, 0.3" SOIC Notes: 1. 2. 3.
UNIT V mA pF V V V mA mW
CONDITIONS RL = 5k, VDD = 4.75V Note 7 No Oscillation IOH = -0.4mA IOL = 1.5mA To rated specifications PR = LOW PR = LOW
C C C
Note 8
4.
5. 6. 7. 8.
Code dependent All VIN(x) = GND; D = 55H Offset binary refers to the output voltage with respect to the signal ground at VREFL. For a positive VIN(x), the output will increase from negative fullscale to VREFL to positive (fullscale-1 LSB) as the input code is incremented from 0 to 128 to 255. Note that when VIN(x) is tied to ground and VREFL is driven to +1.625V, as in the production tests above, then the resulting DC at VOUT(x) will decrease from +2VREFL to VREFL/128 as the code is increased from 00H to FFH, due to the VIN(x) input being tied negative with respect to VREFL. The op amp limits linearity for VOUT <100mV. When VIN(x) is driven above ground such that the output voltage remains above 100mV, then the linearity specifications apply to all codes. For VREFL=1.625V, and VIN(x)=GND, codes 248 through 255 are not included in differential or integral linearity tests. Integral and differential linearity are computed with respect to the best fit straight line through codes 0 through 248. SP9840 is measured between adjacent channels, F=100kHz. SP9843 is measured between adjacent pairs, F=100kHz. SP9843 only; measured between channels with shared input; D = 7FH to 80H VOUT < 10mV, VREFL = 1.625V, PR = LOW. For plastic DIP, consult factory
259
SP9840 PINOUT
VOUTC 1 VOUTB 2 VOUTA 3 VINB 4 VINA 5 VREFL 6 PRESETL VINE VINF 7 8 24 VOUTD 23 VINC 22 VIND 21 VDD 20 SDI 19 GND 18 SDO CLOCK LOADH VINH VING 13 VOUTH 17 16 15 14
Pin17--CLOCK--SerialClockInput;positive-edge triggered. Pin18--SDO--SerialDataOutput;activetotem-pole output. Pin 19 -- GND -- Ground. Pin 20 -- SDI -- Serial Data Input. Pin 21 -- V -- Positive 5V Power Supply.
DD
SP9840
9 VOUTE 10 VOUTF 11 VOUTG 12
Pin 22 -- V D -- DACD Reference Voltage Input.
IN
Pin 23 -- V C -- DACC Reference Voltage Input.
IN
Pin 1 -- V C -- DACC Voltage Output.
OUT
Pin 24 -- V D -- DACD Voltage Output.
OUT
Pin 2 -- V B -- DACB Voltage Output.
OUT
Pin 3 -- V A -- DACA Voltage Output.
OUT
SP9843 PINOUT
VOUTC 1 VOUTB 2 VOUTA 3 VINA/B 4 VREFL 5 PRESETL 6 VINE/F 7 VOUTE 8 VOUTF 9 VOUTG 10 20 19 18 17 16 15 14 13 12 11 VOUTD VINC/D VDD SDI GND SDO CLOCK LOADH VING/H VOUTH
Pin 4 -- V B -- DAC B Reference Voltage Input.
IN
Pin 5 -- V A -- DAC A Reference Voltage Input.
IN
Pin 6 -- V L -- DAC Reference Voltage Input Low, common to all DACs.
REF
SP9843
Pin 7 -- PRESETL -- Preset Input; active low; all DAC registers forced to 80 .
H
Pin 8 -- V E -- DAC E Reference Voltage Input.
IN
Pin 1 -- V C -- DACC Voltage Output. Pin 9 -- V F -- DAC F Reference Voltage Input.
IN OUT
Pin 2 -- V B -- DACB Voltage Output.
OUT
Pin 10 -- V E -- DACE Voltage Output.
OUT
Pin 3 -- V A -- DACA Voltage Output.
OUT
Pin 11 -- V F -- DACF Voltage Output.
OUT
Pin 12 -- V G -- DACG Voltage Output.
OUT
Pin 4 -- V A/B -- DACA and B Reference Voltage Input.
IN
Pin 13 -- V H -- DACH Voltage Output.
OUT
Pin 5 -- VREFL -- DAC Reference Voltage Input Low, common to all DACs. Pin 6 -- PRESETL -- Preset Input; active low; all DAC registers forced to 80 .
H
Pin 14 -- V G -- DACG Reference Voltage Input.
IN
Pin 15 -- V H -- DACH Reference Voltage Input.
IN
Pin 16 -- LOADH -- Load DAC Register Strobe; active high input that transfers the data bits from the Serial Input Register into the decoded DAC Register. Refer to Table 1. 260
Pin 7 -- V E/F -- DAC E and F Reference Voltage Input.
IN
Pin 8 -- V E -- DACE Voltage Output.
OUT
Pin 9 -- V F -- DACF Voltage Output.
OUT
Pin 10 -- V G -- DACG Voltage Output.
OUT
Pin 11 -- V H -- DACH Voltage Output.
OUT
Pin 12 -- V G/H -- DACG and H Reference Voltage Input.
IN
Each channel consists of a voltage-output DAC, realized using CMOS switches and thin-film resistors in an inverted R-2R configuration. Each DAC drives the positive terminal of an op amp, configured for a gain of -1 to +1 using equal value thin-film feedback and gain-setting resistors. Signal return is the VREFL pin, the common reference input return for the eight DAC-op amp channels. As shown in Figure 1, the DAC section can be thought of as a potentiometer across VIN(X) to VREFL. If this potentiometer is set to its minimum value of 0/256, the potentiometer will have no effect on the gain, and the output will be -RF/RIN = -1 times the input. If the potentiometer could be set to 256/256, then the amplifier positive terminal would see 100% of any input and no current would flow through RIN. The circuit would behave as a non-inverting unity gain circuit, although with a noise gain of two, not one. In reality, the "potentiometer" can only be set to 255/256, and the maximum positive gain is 0.992 times the voltage between VIN(X) and VREFL. The true relation between the DC levels at the VIN(X) pins, VREFL and the output can be described as:
VOUT = D ((128 ) - 1) V
( IN
Pin 13 -- LOADH -- Load DAC Register Strobe; active high input that transfers the data bits from the Serial Input Register into the decoded DAC Register. Refer to Table 1. Pin14--CLOCK--SerialClockInput;positive-edge triggered. Pin15--SDO--SerialDataOutput;activetotem-pole output. Pin 16 -- GND -- Ground. Pin 17 -- SDI -- Serial Data Input. Pin 18 -- V -- Positive 5V Power Supply.
DD
Pin 19 -- V C/D -- DACC and D Reference Voltage Input.
IN
Pin 20 -- V D -- DACD Voltage Output.
OUT
- VREFL ) + VREFL
F1
SP9840/SP9843 Theory of Operation Each of the eight channels of the SP9840/9843 can be used for signal reconstruction, as a programmable DC source, or as a programmable signed attenuator of -1 to +0.992 times a multiplying AC reference input. The rugged wideband output amplifiers provide both current sink and source capability to DC applications, even into difficult loads. The DC source mode mimics the functionality of a programmable trimpot, with the added benefit of a low-impedance buffered output. The amplifier's bandwidth and high open loop gain allow use in programmable signed attenuator applications where even low-distortion, high resolution signals, such as audio, must be gated on and off, programmable phase shifted by 0 or 180 or gain controlled over a -42 to 0dB range at either phase.
where D is programmable from 0 to 255. For single supply operation VREFL is usually externally driven to some voltage above ground -- typically 1.5 to 2.5V. IF VREFL is driven to 1.5V, and VIN(X) is grounded, then code 0 would output +3.0V, and code 255 would output +11.7mV. If VREFL were grounded and VIN(X) driven to 1.5V, then codes between 0 and 128 would attempt to drive the output below ground, which will saturate the output amplifier at some voltage slightly above ground.
USING THE SP9840/9843 Multiplication of Input Voltages While both the SP9840 and SP9843 are capable of four-quadrant multiplication, this terminology is not 261
LAST D0 LSB D1 D2 D3 D4 D5 D6 D7 A0 A1 A2
FIRST A3 MSB
DATA
MSB LSB
ADDRESS
A3 0 0 0 0 0 0 0 0 1 1 . . 1 D7 D6 D5 D4 D3
A2 0 0 0 0 1 1 1 1 0 0 . . 1 D2
A1 0 0 1 1 0 0 1 1 0 0 . . 1 D1
A0 0 1 0 1 0 1 0 1 0 1 . . 1 D0
DAC Updated No Operation DACA DACB DACC DACD DACE DACF DACG DACH No Operation . . No operation DAC Output Voltage VOUT =
D - 1 (VIN - VREFL ) + VREF 128
0 0
0 0
0 0
0 0
0 1 1
1 0 0
1 0 0
1 0 0
1 1
1 1
1 1
1 1
0 0 . . . 1 0 0 . . . 1 1
0 0
0 0
0 1
-2VREFL
1 0 0
1 0 0
1 0 1
1 1
1 1
0 1
Table 1. Serial Input Decoded Truth Table
very precise when describing a system which runs from a single positive supply. Traditionally, the quadrants have been defined with respect to 0V. A two- quadrant multiplying DAC could produce negative output voltages only if a negative voltage reference were applied. A four-quadrant device could also produce a code-controlled negative output from a positive reference, or a code-controlled positive output from a negative reference. If ground is used to delineate the quadrants, then the SP9840/SP9843 should be considered single-quadrant multiplying devices, as their output op amps cannot produce voltages below ground.
+5V
In reality, it is possible to define a DC voltage as a signal ground in a single supply system. If the DAC's VREFL pin is driven to the voltage chosen as pseudo- ground, then each voltage output will exhibit 4- quadrant behavior with respect to pseudoground. For codes greater than 128, the output voltage will enter the quadrant below the pseudoground voltage when the input voltage goes below pseudoground. For codes less than 128, the output voltage will be below pseudoground when the input is above pseudoground. When VREFL is driven to some positive voltage and VIN(X) is grounded, the device performs as if it were a buffered trimpot tied between ground and a voltage equal to two times VREFL. This mode of operation can be used as an "inverted single- quadrant" source with an approximate range of 0 to (VREFL*2)Volts. Because the output voltage will decrease as the code is increased, this mode is considered to be inverted with respect to normal single-quadrant operation. Note that the minimum output voltage will be 1LSB above VIN(X). Figure 2a and 2b show "inverted single-quadrant" and 4-quadrant performance of the SP9840/9843.
VDD VIN(X)
- +
VOUT DAC
VREFL
3 VOUT = D - 1 (VIN -VREFL ) + VREFL
128
Figure 1. DAC and Output Amplifier Circuit
262
a) Figure 2. a) Inverted Single-Quadrant Operation; b) 4-Quadrant Operation
b)
Applications which require two-quadrant operation with respect to pseudoground should use the SIPEX SP9841 or SP9842 two-quadrant multiplying DACs. The choice of voltage to use for the pseudoground is limited by the legal voltage swing at the op amp output. The op amp exhibits excellent linearity for output voltages between, conservatively, 100mV and VDD - 1.5V. The op amp BiCMOS output stage consists of an npn follower loaded by an NMOS common sourced to ground. This circuit exhibits wide bandwidth and can source large currents, while retaining the capability of driving the output to voltages close to ground. At output voltages below 25mV, feedback forces some op amp internal nodes toward the supply rails. The NMOS pull-down device gets driven hard and the NMOS device enters the linear region -- it begins to function in the same manner as a 50 ohm resistor. In reality, the wideband amplifier output stage sinks some internal quiescent current even when driving the output towards ground. This sunk current drops across the output stage NMOS transistor ON- resistance and internal routing resistance to provide a minimum output voltage below which the
SDI X Data X X X L CLK L LOADH L L X H PRESETL H H L H
amplifier cannot drive. This minimum voltage is in the 15 to 25mV range. It varies within a package with each op amp's offset voltage and biasing variations. If an input voltage lower than this minimum, such as code 255 when VIN(X) is grounded, is requested, feedback within the op amp circuit will force internal nodes to the rails, while the output will remain saturated near this minimum value. Non-saturated monotonic behavior returns between 25mV and 100mV at the output, but full open loop gain and linearity are not apparent until the output voltage is nearly 100mV above the negative supply. Four-quadrant (programmable signed attenuator) applications usually bias V REFL up at system pseudoground, well above this saturation region, and therefore maintain linearity even at high attenuations (i.e. near code 80HEX). Driving the Reference Inputs The eight independent VIN inputs of the SP9840, and the four-pair of inputs in the SP9843, exhibit a code- dependent input resistance, as shown in the specifications, and as a typical graph. In general, these inputs should be driven by an amplifier capable of handling
LOGIC OPERATION No Change Shift In One Bit from SDI Shift Out 12-clock delayed data at SDO All DAC Registers Preset to 80H (Note 1) Load Serial Register Data into DAC(X) Register
Note 1: "Preset" may not persist at all DACs if LOADH is high when PRESETL returns high. Table 2. Logic Control Input Truth Table.
263
the specified load resistance and capacitance. The reference inputs are useful for both AC and DC input sources. However, series resistance into these pins will degrade the linearity of the DAC -- 50 Ohms of series resistance can cause up to 0.5LSB of additional integral linearity degradation for codes near zero, due to the code-dependent input current dropping across this error resistance. AC-coupled applications should use the largest capacitor value (lowest series impedance) which is practical, or use an external buffer to drive the inputs. The DAC switches function in a break-before-make manner in order to minimize current spikes at the reference inputs. The reference inputs can withstand driving voltages slightly beyond the power rails without harm; the gain of 1 at the op amps limits the choice of VIN/VREFL combinations if clipping is to be avoided at very high or very low codes. Note that rail- to-rail inputs can always be attenuated by choosing a code nearer midscale, if clipping of the output is undesirable. Output Considerations Each DAC output amplifier can easily drive 1Kohm loads in parallel with 15pF at its rated slew rate. The unique BiCMOS amplifier design also ensures stability into heavily capacitive loads -- up to 47,000pF. Under these conditions, the slew rate will be limited by the instantaneous current available for charging the capacitance -- the slew rate will be severely degraded, and some damped ringing will occur. Especially under heavy capacitive loading, a large, low impedance local bypass capacitor will be required. A 0.047F ceramic in parallel with a low-ESR 2.2 to 10F tantalum are recommended for worst-case loads. The amplifier outputs can withstand momentary shorts to VDD or ground. Continuous short circuit operation can result in thermally induced damage, and should be avoided. If the input reference voltage is reduced to 0.6V, then both the amplifier and DAC are functional at room temperature at supply voltages as low as 2.5V. At VDD = 2.7V, power dissipation is 9.3mW typical, with the serial clock at 4MHz, or 7.0mW typical with the serial clock gated off.
Interfacing to the SP9840/SP9843 A simple serial interface, similar to that used in a 74HC594 shift-register with output latch, has been implemented in these products. A serial clock is used to strobe serial data into a 12-stage shift-register at each rising clock edge. The first four serial bits contain the address of the DAC to be updated, MSB first. The next 8 bits contain the binary value to be loaded into the desired DAC, again MSB first. After the 12th serial bit is clocked in, the LOADH line can be strobed to latch the 8 bits of data into the data holding register for the desired DAC. The address bits feed a decoding network which steers the LOADH pulse to the clock input of the desired DAC data holding register. The output of the 12th shift-register is also buffered and brought out as the SERIAL DATA OUT (SDO), which can be used to cascade multiple devices, or for data verification purposes. The address field is set up such that DACA is addressed at 0001 (binary) and the others consecutively through DACH at 1000(binary). Address 0000(binary) will not affect the operation of any channel, as this combination is easily generated inadvertently at power-up. Other no-operation addresses exist at 1001(binary) through 1111(binary). Another use for no-operation addresses is to mask off updates of any DAC channel in a multiple-part system with cascaded serial inputs and outputs. By sending a valid address and data only to the desired channel, it is possible to simplify the system hardware by driving the LOADH pin at each part in parallel from a single source. Table 1 shows a register-level diagram of the addresses, data, and the resulting operation. A fourth control pin, PRESETL, can be used to simultaneously preset all DAC data holding registers to their mid-scale (80H) values. This will asynchronously force all DAC outputs to buffer the voltages at their respective inputs to their outputs with unity gain. This feature is useful at power-up, as a simple resistor to the supply and capacitor to ground can insure that all DAC outputs start at a known voltage. For four- channel multiplying applications, this sets the default start-up gain to zero; only -70dB of feedthrough from the VIN(X) inputs will be present at the outputs. Table 2 summarizes the operation of the four digital inputs.
264
The four digital control input pins have been designed to accept TTL (0.8V to 2.0V minimum) or full 5V CMOS input levels. The serial data output can drive either TTL or CMOS inputs. Timing information is shown in Figure 3. Serial data is fully clocked into the shift-register after 12 clock rising edges, subject to the described setup and hold times. After the shift-register data is valid, the LOADH line can be pulsed high to load data into the desired DAC data register, which switches the DAC to the new input code. The serial clock input should not see a rising edge while the LOADH pulse is high in order to prevent shift-
tPR tS
register data from corruption during data register loading. The serial clock and data input pins are designed to be compatibleasslavesunder NationalSemiconductor's MicrowireTM and MicrowirePlusTM protocols and under Motorola's SPITM and QSPITM protocols. In some micro-controllers, the interface is completed by programming a bit in a general-purpose I/O port as a level, used to strobe the LOADH line at the DACs. This is done in a manner similar to that used for generating a Chip Select signal, which is necessary when driving some other MicrowireTM peripherals.
PRESET
1 0
VOUT (FFH) (08H)
1 0 1 0 1 0
1 LSB ERROR BAND
A0 D7 D6 D5 D4 D3 D2 D1 D0
SDI
A3
A2
A1
CLOCK LOAD
VOUTFS 0
SERIAL DATA INPUT TIMING DETAIL (PRESET = Logic "1"; VIN(X) = 1.5V; VREFL = 0V) SERIAL 1 DATA IN 0 SERIAL 1 DATA OUT 0 CLOCK LOAD 1 0 1 0 tCH tCL AX or DX tDS tDH tPD tCLKD tLD tS 1 LSB ERROR BAND tLDCK
VOUT (FFH) (08H)
CHARACTERISTICS
(Typical @ 25C with VDD = +5V unless otherwise noted.)
PARAMETER Input Clock Pulse Width (tCH, tCL) Data Setup Time (tDS) Data Hold Time (tDH) CLK to SDO Propagation Delay (tPD) DAC Register Load Pulse Width (tLD) Preset Pulse Width (tPR) Clock Edge to Load Time (tCKLD) Load Edge to Next Clock Edge (tLDCK) Figure 3. Timing
MIN. 50 30 20 50 50 30
TYP.
MAX.
100
60
UNIT ns ns ns ns ns ns ns ns
CONDITIONS
265
ORDERING INFORMATION
Model SP9840KN SP9840BN SP9840KS SP9840BS SP9843KS SP9843BS Reference Inputs Temperature Range Package ................................... Eight, independent ............................................... 0 to + 70C ................................. 24-pin, 0.3" Plastic DIP ................................... Eight, independent ............................................... -40 to + 85C ............................. 24-pin, 0.3" Plastic DIP ................................... Eight, independent ............................................... 0 to + 70C ........................................... 24-pin, 0.3" SOIC ................................... Eight, independent ............................................... -40 to + 85C ....................................... 24-pin, 0.3" SOIC ................................... Four pair ............................................................... 0 to + 70C ........................................... 20-pin, 0.3" SOIC ................................... Four pair ............................................................... -40 to + 85C ....................................... 20-pin, 0.3" SOIC
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